The Department of Nuclear and Particle Physics (DPNC) at the University of Geneva invites applications for an engineer to join the ATLAS Trigger and Data Acquisition (TDAQ) upgrade project, specifically focusing on implementing low-latency algorithms into FPGA and heterogeneous computing systems for the HL-LHC upgrade. The DPNC has made substantial contributions to the ATLAS experiment and is actively involved in the HL-LHC upgrades of both the ATLAS tracker and TDAQ systems.

The successful candidate will work on the integration of algorithms into FPGA and heterogeneous systems for the Event Filter in the ATLAS TDAQ upgrade. These systems will process data at a real-time rate of 1 MHz, selecting 1% of the events for storage using fast, low-latency algorithms. The role will focus on optimizing and implementing these algorithms on FPGA-based accelerators. Low-latency (μs) implementation of algorithms in the Global trigger processor may also be pursued.

Key tasks will include working with FPGA accelerators (e.g., Xilinx Versal cards) to integrate hadronic reconstruction-related algorithms into a high-performance computing system designed to meet the ATLAS TDAQ HL-LHC performance requirements. The tasks will involve supporting low-latency processing for the Global Trigger Processor. 

The engineer will work closely with a team of physicists and engineers from the University of Geneva and other institutes involved in the ATLAS TDAQ upgrade.

* Implement and optimize existing algorithms (including ML-based algorithms) for FPGA-based systems and heterogeneous computing architectures (e.g., Xilinx Versal FPGAs)

* Conduct system integration, performance evaluation, and benchmarking to ensure the algorithms work efficiently within the overall TDAQ system.

* Integrate reconstruction algorithms (e.g., topoclustering) to the Global trigger processor meeting low-latency constraints.

* Collaborate with physicists, engineers, and researchers from international institutes working on the ATLAS TDAQ HL-LHC upgrade.

* Master’s degree in Computer Science, Engineering, or a related field.

* Strong experience with FPGA prototyping, hardware acceleration, and heterogeneous computing systems.

* Familiarity with FPGA tools (e.g., HLS, Vivado) or hardware description languages (e.g., VHDL or Verilog).

* Proven experience implementing algorithms onto hardware systems.

* Proficiency in English with excellent oral and written communication skills.

* Ability to work autonomously and collaboratively in an international research environment.

* Experience with FPGA acceleration and hardware-software co-design.

* Knowledge of version control systems (e.g., GitHub).

* Familiarity with machine learning algorithms and their implementation on hardware. 

* Experience in high-performance computing and real-time systems.

The position is available immediately. The position is to be filled as soon as a suitable candidate is selected. The succesful candidate will be offered an initial 1-year contract, with extensions possible depending on funding availability. Funding is currently guaranteed until end of March 2027.

This is an exciting opportunity to work on the integration of cutting-edge low-latency algorithms into FPGA-based and heterogeneous computing systems, contributing to one of the most significant upgrades in the ATLAS experiment’s history. You’ll work in a dynamic, international environment alongside world-class researchers in particle physics and high-performance computing.