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Abstract: (IEEE)
Frond-end electronics at the High Luminosity-Large Hadron Collider (HL-LHC) at CERN, will be exposed to ten-fold radiation doses. The use of enclosed gate (EG) MOSFETs of 65 nm Bulk CMOS process, is considered to be a viable solution in order to suppress performance degradation effects that occur after high TID exposure. The present paper presents a detailed analysis of the functionality of EG MOSFETs operating under high TID, taking into accountspecific layout characteristics.
  • MOS devices
  • Threshold voltage
  • Integrated circuits
  • Logic gates
  • Hafnium
  • CMOS integrated circuits
  • MOSFET
  • radiation hardening (electronics)
  • frond-end electronics
  • High Luminosity-Large Hadron Collider