Data Formatter Design Specification: DRAFT Version 0.1

Collisions in the LHC occur at the nominal rate of 40MHz with a design luminosity of 1 × 1034 and approximately 25 overlapping proton-proton interactions per crossing. The ATLAS detector trigger system must reject a vast majority of these events, and only 200 events per second can be stored for later analysis. An upgrade to the LHC is in the planning stages. Instantaneous luminosity is expected to increase to 3×1034 with an average of 75 proton-proton interactions per crossing. Under these conditions the existing ATLAS trigger is strained and the need for a tracking trigger is clear. The Fast Tracker (FTK) proposal involves adding a hardware-based level-2 track trigger to the ATLAS DAQ system. The FTK proposal includes a Data Formatter system to remap the ATLAS inner detector geometry to match the FTK − towers. The Data Formatter system also performs pixel clustering and data sharing in overlap regions. This design specification describes the Data Formatter system in detail and chronicles the “bottom up” approach to hardware design. Based on the current design requirements and the need for future expansion capabilities, a full mesh backplane interconnect is a natural fit for the Data Formatter design. Our final design also works well as a general purpose FPGA-based processor board. The Data Formatter may prove useful in scalable systems where highly flexible, non-blocking, high bandwidth board to board communication is required.

tracks: trigger
ATLAS
data acquisition
upgrade
electronics: design
FPGA
programming
data management

References(13)

Figures(0)

[1]

ATLAS Experiment at CERN Geneva, Switzerland

- http://atlas.ch

[2]

Fermi National Accelerator Laboratory Batavia, Illinois 60510 USA

- http://www.fnal.gov

[3]

Clustering Algorithm Based on FPGAs for High-Throughput Data Processing A. Annoiv and M. Beretta INFN - Laboratori Nazionali di Frascati, via E. Fermi 40, Frascati