Vertically Integrated Circuit Development at Fermilab for Detectors

Today vertically integrated circuits, (a.k.a. 3D integrated circuits) is a popular topic in many trade journals. The many advantages of these circuits have been described such as higher speed due to shorter trace lenghts, the ability to reduce cross talk by placing analog and digital circuits on different levels, higher circuit density without the going to smaller feature sizes, lower interconnect capacitance leading to lower power, reduced chip size, and different processing for the various layers to optimize performance. There are some added advantages specifically for MAPS (Monolithic Active Pixel Sensors) in High Energy Physics: four side buttable pixel arrays, 100% diode fill factor, the ability to move PMOS transistors out of the diode sensing layer, and a increase in channel density. Fermilab began investigating 3D circuits in 2006. Many different bonding processes have been described for fabricating 3D circuits [1]. Fermilab has used three different processes to fabricate several circuits for specific applications in High Energy Physics and X-ray imaging. This paper covers some of the early 3D work at Fermilab and then moves to more recent activities. The major processes we have used are discussed and some of the problems encountered are described. An overview of pertinent 3D circuit designs is presented along with test results thus far.

activity report
integrated circuit: design
semiconductor detector: pixel
electronics: readout
dimension: 3
history
Fermilab

References(9)

Figures(0)

[1]

Handbook of 3D Integration, Vol 1 & 2 2008

P. Garrou
,
C. Bower
,
P. Ramm

[2]

A vertically integrated pixel readout device for the vertex detector at the International Linear Collider Trans. on Nuclear

G. Deptuch

- Science 57 (2010) 880

[3]

The first multi-project run with Chartered/Tezzaron, Proceedings of Front End Electronics Meeting 2011, Bergamo Italy

R. Yarema

[4]

Metal wafer bonding for MEMS devices. Romanian Journal of information Science and Technology, vol 13, no 1, 2010, p 69

V. Dragoi

[5]

Direct Bond Interconnect - Technology for scaleable 3D SoCs, 3D Architectures for Semiconductor Integration and Packaging, 2006, San Francisco

P. Enquist

[6]

Direct measurement of antiferromagnetic domains

O.G. Shpyrko

- Nature 447 (2007) 68

[7]

MEPHISTO binary readout architecture for strip detectors, NIMA 461, pp 499-504

P. Fisher

[8]

First Three dimensional integrated chip for photon science, presented at Vertex 2012

P. Maj

[9]

Vertically integrated pattern recognition associative memory for track finding, presented at TWEPP 2012

J. Hoff