SVX4: A New Deep-Submicron Readout IC for the Tevatron Collider at Fermilab

SVX4 is the new silicon strip readout IC designed to meet the increased radiation tolerance requirements for Run IIb at the Tevatron collider. Devices have been fabricated, tested, and approved for production. The SVX4 design is a technology migration of the SVX3D design currently in use by CDF. Whereas SVX3D was fabricated in a 0.8-μm radiation-hard process, SVX4 was fabricated in a standard 0.25-μm mixed-signal CMOS technology using the "radiation tolerant by design" transistor topologies devised by the CERN RD49 collaboration. The specific cell layouts include digital cells developed by the ATLAS Pixel group, and full-custom analog blocks. Unlike its predecessors, the new design also includes the necessary features required for generic use by both the CDF and D0 experiments at Fermilab. Performance of the IC includes >20 MRad total dose tolerance, and ∼2000 e-rms equivalent input noise charge with 40-pF input capacitance, when sampled at 132-ns period with an 80-ns preamp risetime. At the nominal digitize/readout rate of 106/53 MHz, the 9 mm×6.3 mm die dissipates ∼2 mW/channel average at 2.5 V. A review of typical operation, details of the design conversion process, and performance measurements are covered.

References(10)

Figures(0)

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Diva LVS is a Cadence Design Systems EDA IC verification tool. SVX4 SVX3D Die size 6.3 x 9 mm. 6.3 x 12.3 mm. Power supply voltage 2.5 V 5 power per ch 2 mW 2 mW Preamp gain 5 mV/fC 5 mV/fC Dynamic range 60 fC 80 fC Overall gain (nominal) 0.15 fC/bit 0.15 fC/bit Digitize speed > 212 MHz 106 MHz Readout speed 53 MHz 53 MHz Acquisition period 132 ns. 132 ns. ADC INL/DNL/Noise < 1 LSB < 1 LSB Total dose tolerance > 20 MRad 4 MRad SEU register tolerance < 6 x 10 -17 cm 2 < 6x 10 -16 cm 2

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