FPGA-based Distributed Union-Find Decoder for Surface Codes

Liyanage, Namitha; Wu, Yue; Tagare, Siona; Zhong, Lin

doi:10.1109/TQE.2024.3467271

FPGA-based Distributed Union-Find Decoder for Surface Codes

Mar 20, 2024

e-Print:

2406.08491 [quant-ph]

DOI:

10.1109/TQE.2024.3467271 (publication)

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Abstract: (arXiv)

A fault-tolerant quantum computer must decode and correct errors faster than they appear to prevent exponential slowdown due to error correction. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than

O(d^3)

. We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to

d

, given

O(d^3)

parallel computing resources. The decoding time per measurement round decreases as

d

increases, the first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. Using a Xilinx VCU129 FPGA, we successfully implement

d

up to 21 with an average decoding time of 11.5 ns per measurement round under 0.1% phenomenological noise, and 23.7 ns for

d=17

under equivalent circuit-level noise. This performance is significantly faster than any existing decoder implementation. Furthermore, we show that Helios can optimize for resource efficiency by decoding

d=51

on a Xilinx VCU129 FPGA with an average latency of 544ns per measurement round.

Note:

The article extends the work in arXiv:2301.08419, which also appeared in https://ieeexplore.ieee.org/document/10313800

References(36)

Figures(16)

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VOLUME x, xxxx 15 Algorithm 8: FPGA-oriented controller logic 162 global_stage ← growing 163 At every positive clock edge do 164 if global_stage = growing then 165 global_stage ← merging 166 %Wait until all PEs are in Merging Stage 167 Wait 2 clock cycles 168 end 169 else if ∀v ∈ V, v.busy = false then 170 if ∀v ∈ V, v.codd = false then 171 global_stage ← terminate