Scalable Quantum Error Correction for Surface Codes Using FPGA - INSPIRE

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Scalable Quantum Error Correction for Surface Codes Using FPGA

Jan 19, 2023

12 pages

Contribution to:

- QCE23
, 916-927

Published: Sep 17, 2023
and
Published: May, 2023

e-Print:

2301.08419 [quant-ph]

DOI:

View in:

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Abstract: (IEEE)

A fault-tolerant quantum computer must decode and correct errors faster than they appear. The faster errors can be corrected, the more time the computer can do useful work. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than

O(d^{3}

. We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder has

a

sublinear average time complexity with regard to

d

given

O(d^{3}

parallel computing resources. The decoding time per measurement round decreases as

d

increases, a first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. We are able to implement

d

up to 21 with a Xilinx VCU129 FPGA, for which an average decoding time is 11.5 ns per measurement round under phenomenological noise of 0.1 %, significantly faster than any existing decoder implementation. Since the decoding time per measurement round of Helios decreases with d, Helios can decode a surface code of arbitrarily large

d

without a growing backlog.

Codes
Fault tolerance
Quantum computing
Measurement uncertainty
Systems architecture
Fault tolerant systems
Parallel processing
Time measurement
Decoding
Scalable

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